Fan-out Wafer Level Packaging Research Articles

Research of Chip Placement Accuracy for Fan-Out WLP using A Novel Self-Assembly Stage

This paper discusses the alignment accuracy after self-assembly using a novel self- assembly method with a uniquely developed porous stage. In a preceding paper, we have introduced our process that combines tape expansion technology and self-assembly technology. By using this process and machine device, it is possible to significantly improve the throughput of pick and place process for FO-WLP. Furthermore, it is indicated that our self-assembly method using the porous chuck stage enables achievement of high precision chip alignment and high throughput. In this study, two factors are evaluated to clarify the impact on the chip accuracy after self-assembly; 1) the influence of chip position before self-assembly, 2) the relationship between stage size of self-assembly area and chip size. As a result of evaluation, if the chip size is the same as the porous stage size, the alignment accuracy after self-assembly is within 5 μm or less even with varied chip positions before self-assembly. On the other hand, when the porous stage size and chip size are different, the chip position before self-assembly has an impact on the alignment accuracy after self-assembly. Based on the results obtained in this study, further development of machine device and process will be pursued to improve the alignment accuracy after selfassembly.

High-Q Ku-band Microstrip Spiral Resonator in Fan-out Wafer-Level Packaging (FoWLP) Technology for VCO Applications

In this paper, a planar spiral resonator operating at 13 GHz is investigated. The resonator was fabricated using fan-out wafer level packaging (FoWLP) technology. The field analysis highlights the importance of via fence. Two thick film resistors suppress an undesired resonance in proximity of targeted one. The measurements demonstrate a very good correlation in comparison with full-wave simulations. The measured Q-factor defined based on analysis of feedback oscillatory system is about 48. The proposed configuration is suitable for voltage-controlled oscillators (VCOs) with a resonator realized in package.

Characterizations for eWLB (Embedded Wafer Level Ball Grid Array) Antenna in Molded Package Integrations in 77GHz Automotive Applications

The worldwide IC market has had a significant growth rate in recent years, driving diversified package solutions in the segments of communication, computing, consumer, automotive, industrial, etc. Among these market segments, the automotive market is forecast to have the strongest CAGR (Compound Annual Growth Rate) of any of the end-use segments in the next 5 years, which results in more IC packages and components being designed into automotive vehicle systems such as infotainment, ADAS (Advance Driving Assistance System), instrumentation, body systems, battery control systems and so on. In these applications, the 77GHz short-range radar sensor application that can enable higher EIRP (Effective Isotropic Radiated Power) and adaptive cruise control performance has become more attractive to be commercialized. Due to the benefits of shorter interconnection length, lower conductive loss with smooth Cu surface as well as a lower dielectric constant and dielectric loss of materials in a fan-out wafer level package (FOWLP) technology, the FOWLP is proven as a suitable packaging solution to achieve the high speed and frequency requirements in 5G and mmWave applications. The eWLB Embedded Wafer Level Ball Grid Array) is a versatile FOWLP technology, providing a robust package platform in a space-efficient design with the very dense interconnection and routing of multiple dies as well as a smaller footprint and lower package profile providing a reliable package solution. Meanwhile, since the utilization of an antenna that is integrated into the packages has been studied as a lowcost solution because the packages can be tested in normal FR4 printed circuit board (PCB) instead of the RF function integrated PCB, the eWLB integrated with molded antenna chip packages (called eWLB antenna in molded package) technology is introduced in this paper. The characterizations for assembly process challenges are evaluated and illustrate the process optimizations of equipment handling, antenna molded chip package fabrication, reconstitution process control and warpage characterization of the molded wafer. In addition, the radio frequency (RF) test validation is performed to verify the performance of scattering parameter (S-parameter), radiation pattern, impedance and detection range of the antenna. In order to prove the reliable quality and yield of the evaluated eWLB antenna in molded packages, package-level reliability tests are studied. Through these results, it will show that this eWLB antenna in molded package integration is a robust and costeffective solution for 77GHz automotive applications.

Addressing Die Displacement in Lithography Processes for Advanced Packaging Applications

To perpetuate Moore’s Law, semiconductor manufacturers are adopting advanced packaging technology as the mainstream solution. As a result, today, fan-out wafer level packaging is a key enabler of two- and three-dimensional packaging solutions. Among the manufacturing challenges, die displacement in lithography processes has been widely discussed, but a total solution is yet to come. In this study, we demonstrate die-by-die and global wafer alignment strategies available on-board the Kulicke & Soffa LITEQ 500 projection stepper. The versatility of a die-by-die alignment strategy allows for working with reconstituted wafers without resorting to an external metrology tool. The die displacement residuals can be reduced by three orders of magnitude, typically, from 100um to 100nm. The evaluation of overlay accuracy by implementing a die-by-die and global wafer alignment strategy indicates comparable performances. Considering high volume manufacturing, advanced process control of overlay is also capable of applying to a batch of wafers.

Cleaning and Particle Challenges in the Temporary Bonding and Debonding Process

The demands of 5G, Internet of Things and other global technology trends, combined with the increasing cost of scaling down process nodes, have created a shift towards more integrated packaging requirements. The emergence of advanced packaging technologies, such as Fan-Out Wafer Level Packaging (FOWLP), 2.5D/3D IC packaging, and heterogenous integration, brings potential for smaller form factors with increased functionality and bandwidth [1]. Backside processing or thinning of the device wafer is often needed for enabling these technologies. This requires the device wafer be adhered to a rigid carrier wafer using a temporary bonding material (TBM) for mechanical support during handling and processing. Following carrier release, the TBM must be thoroughly removed and cleaned from the device wafer. Many of these adhesives are exposed to high-power lasers or elevated temperatures, making removal more challenging. Sub-micron particle level clean demands for temporary bonding material (TBM) removal are also reaching standards typically reserved for front-end-of-line (FEOL) processing. This is especially crucial in 3D processes such as hybrid bonding where feature and pitch sizes are nearing <1 µm and insufficient cleaning can lead to failures in subsequent bonding processes [2]. Thus, careful consideration of all processing steps is necessary to meet stringent particle demands. This work investigates the removal of coated and baked TBM on silicon wafers, with an emphasis on processing conditions that obtain best particle results. Several chemistries were assessed at the beaker level by performing coupon-level studies and measuring surface properties. Based on these findings, studies with 300-mm wafers were performed using a customizable single-wafer processing tool.

Ultrathin Antenna-in-Package Based on TMV-Embedded FOWLP for 5G mm-Wave Applications

In this paper, a novel through mold via (TMV)-embedded fan-out wafer-level package (FOWLP) technology was demonstrated to manufacture the well-designed Antenna in Package (AiP) with ultrathin thickness (0.04 λ0). Double-sided redistribution layers (RDLs) were employed to build the patch antenna, while a TMV interposer was used to connect the front and back RDLs. By optimizing the AiP’s parameters, the patch antenna can achieve a wide impedance bandwidth of 17.8% from 24.2 to 28.5 GHz, which can cover the 5G frequency bands. Compared with previous works, the proposed AiP has significant benefits in terms of its ultralow profile, easy processing, and high gain. Hence, the TMV-embedded FOWLP should be a promising technology for fifth generation (5G) millimeter wave (mm-Wave) applications.

Study on Enhancing Adhesion and Reliability in Wafer-Level Fan-Out Packaging

Study on Enhancing Adhesion and Reliability in Wafer-Level Fan-Out Packaging

FOWLP and Flip Chip Cost Comparison: Impact of the Supply Chain Crunch

The impact of the pandemic on the semiconductor and electronics packaging supply chains has been in the news for over a year now. Current projections suggest the supply chain crunch could impact various industries through 2022 and 2023. While there are many ramifications of this shortage, one is certainly the impact on cost. Pricing for packages built with more mature technologies, such as wire bond and flip chip, has changed dramatically. Both of these mature technologies have typically been seen as lower cost options than newer technologies, such as fan-out wafer level packaging (FOWLP). Due to the recent shortages, the cost comparison is no longer as straight-forward as it was before. This paper will analyze the cost of building various packages using flip chip, wire bond, and FOWLP technologies. Factory overhead, indirect costs, and profit margins will be taken into account to turn this into a price comparison, rather than just a comparison of direct costs. The analyses will include the price of a package built using FOWLP technology, the price of flip chip and wire bond packages built before recent supply chain disruptions, and the new expected prices of flip chip and wire bond packages. Activity based cost modeling will be used for this analysis. This is a bottom-up, detailed approach to cost that accounts for the many cost components associated with every step of the process flow, such as material, labor, and capital depreciation. The goal of this analysis is to understand how supply chain disruptions have changed the cost parity points of wire bond, flip chip, and FOWLP packages.

Improving Reliability of Fan -Out Wafer Level Package Through Doping of Lead-Free Solder Balls

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Doping of Bi and/or Sb was applied to improve the resistance of lead-free SAC balls against thermal cycling stress. We have shown that by increasing the doping level the lifetime can be increased and determined the maximum doping level before extrinsic failure modes dominate. It is well-known from the literature that doping of Bi and/or Sb improves the resistance of lead-free SAC balls against thermal cycling stress. It was shown that lifetime of FC-BGA package can be multiplied using Bi and/or Sb doping. The lifetime gain is achieved by reduced creepage of the hardened balls caused by the doping. This reduced creepage increases the risk of causing other failures than ball cracks in the eWLB package or the PCB during thermal cycling stress. We have tested robustness of 7x8,5 mm^2 eWLB packages against thermal cycling stress T = -40 to 125 °C using SAC-balls with different Bi-doping content from 0% to 2,5% Bi concentration. As could be expected the solder ball fatigue mode is delayed more and more increasing the Bi content. We found other failure modes than solder ball fatigue emerging at doping around 1%. The fatigue modes are shifted towards cupper lines on PCB or into the package. Cu line cracks can be overcome by switching the PCB layout from NSMD (non solder-mask defined) to SMD (solder-mask defined) solder pads. In general there is a lifetime penalty when switching from NSMD to SMD, but by avoiding the Cu line cracks this lifetime loss is overcompensated using SMD pads for optimum performance. As input for simulations we have characterized the doped solder material using specimens produced in glass columns. We have also tested the components on PCBs with different top layer laminate with different CTE and elastic modulus to assess the influence of the PCB properties on the lifetime. It is a trend in automotive radar systems to use stiffer laminates which are cheaper but have negative influence on component lifetime. Solder ball shear tests were also carried out to characterize the influence of ball doping on other board-level reliability beyond thermal cycling performance. As expected ball shear force is increased with increased doping level. At increased shear-force the shearing is still done through the solder ball and does not lead to different shear-mode. Finally drop-tests were done to check influence of doping on board-level reliability performance other than thermal-cycling performance.

Erratum:Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package [IEICE Electronics Express Vol. 19 (2022) No. 14 pp. 20220122]

Erratum:Antenna in package design and measurement for millimeter-wave applications in fan-out wafer-level package [IEICE Electronics Express Vol. 19 (2022) No. 14 pp. 20220122]

Advanced Glass Carriers for Buildup Structure Warp Control and Wafer Ultra-thinning

Tailorable CTE of glass carriers enables effective warp control of buildup structures such as fan-Out wafer level package and multi-layer laminates. Corning’s Advanced Packaging Carrier (APC) product family covers CTE from 4.9-12.6 ppm/C with fine granularity down to 0.2 ppm/C, and other glass types go down in CTE all the way to 0 ppm/C. We illustrate the benefits of having such CTE capabilities using several use cases. Carrier supported wafer thinning down to single digit microns is another emerging need. In addition to CTE matching, such ultra-thinning requires the carrier and the associated temporary bonding method to deliver very low total thickness variation (TTV), typically a small fraction of the final wafer thickness. We will introduce Corning’s recently announced ultra-low-TTV (ULTTV) glass carriers as well as near-zero-TTV temporary bonding methods that enable ultra-thinning of wafers of various types.

A Novel 2D/3D X-ray Microscopy Alignment and Inspection Solution for Thermocompression Bonding (TCB) in a Highly Integrated Flip Chip Fan-Out Wafer Level Package (FO-WLP)

As packaging drives to extend the capabilities of Moore’s Law via heterogenous integration, numerous bonding technologies have emerged as potential pathways, allowing for integration of both a variety of devices in the lateral space as well as vertical integration of chips via stacking. As vertical integration on interposer becomes more complex due to shrinking CDs and increasing die layers, alignment and shape control in the bonding process becomes critical. Thermocompression bonding (TCB) is particularly well-suited for larger die, where localized reflow allows a better control of chip gap height and tilt throughout the bonding process. TCB systems require both high accuracy and repeatability in all dimensions to provide a reliable system in package. While a 2D system can provide a plan view assessment of a single bond layer between two chips, it falls short in characterizing the critical z-dimension in a highly integrated chip stacking scenario. Therefore a robust solution is needed for both system alignment validation in the x,y plane as well as a capability to explore gap height and bump quality/buried issues in high aspect ratio TSV. This paper will explore an x-ray application of a stacked 15-layer die-to-interposer structure to qualitatively validate overall health of the TSV (bond, pad, fill) via a nondestructive volumetric method as well as quantitatively evaluate stacked die for via/ball/pad alignment to determine overall alignment shift during the bonding process. In the test vehicle for a flip chip FO-WLP process flow first presented by IMEC, a silicon (Si) bridge is utilized to connect the logic and through-package via dies with a bump pitch of 20µm for the logic die interconnect. This is done by carefully aligning the logic dies on the carrier and then placing the through-package dies aligned to the carrier and logic dies. In the final step, a high accuracy placement and stacking TCB tool attaches the Si bridge. To perform an accurate assessment for bump alignment and bond quality, an initial high-resolution 3D x-ray scan is performed on a 1.5mm3 region of interest with over 2,000 individual projections at a 1.4µm voxel resolution with a 4x objective, taking approximately two hours. The dataset is put through a deep-learning algorithm which generates an AI model. This model is then applied to a faster scan of 15 minutes with a 1.4µm voxel resolution for the same field of view (FOV) on a nearby array and the data is collected and processed. To verify alignment of the entire sample, data is collected on the tightest pitch (in this case 20µm) oriented in both the vertical (x) and horizontal (y) plane in the through-silicon via (TSV) region. The z-plane is analyzed and processed by computer vision algorithms, and individual interconnects are then quantified and sorted for solder height (z), width (x,y) and TSV misalignment (deviation from expected center, x1y1 → x2y2). To validate the model, a high-resolution uncorrected 20h scan and a 15min scan based on deep learning are collected for the same region of interest (ROI). The data is comparable. Furthermore, the global misalignment data between both datasets demonstrates similar misalignment propagating through the 15-layer stack.

Using M-Series with Adaptive Patterning to shrink PCB systems into System-In-Packages

Traditional system-level design typically includes several Integrated Circuits (IC’s) that get individually packaged and implemented onto a Printed Circuit Board (PCB). This PCB includes the required support circuitry for the IC’s to complete the full system design. This architecture creates a system that is far larger and more power intensive than a single package. It also suffers from greater bandwidth and signal integrity limitations. To counter these shortcomings, many companies are migrating away from PCB to System-in-Package (SiP) designs. In a SiP design, these chips are integrated into a single package along with all the supporting passive devices. The die of the package may be configured through vertical stacking or lateral interconnects to improve design density. For semiconductor companies that design both the IC’s and the system-level PCB, there is an emerging trend in which the existing PCB designs are reused and re-purposed to generate a new SiP design. This allows for companies to leverage known-good design data to create a smaller form factor, higher density package, while requiring fewer engineering design hours. While the prominent solution for SiP designs has been laminate substrates, as the demand for further density scaling and heterogeneous integration grows, advanced packaging technologies are being leveraged. Using a fan-out RDL based solution can accommodate increased interconnect density and reduced layer count as compared to a laminate substrate. Deca’s Adaptive Patterning® technology ensures companies are able to manufacture fan-out wafer-level packages (FOWLP) with the highest possible yield. This paper details the benefits of migrating from PCB to package level integration as well as how utilizing Adaptive Patterning® technology further benefits this migration with increased density and performance as compared to traditional packaging technology

Mask-less Laser Direct Imaging & Adaptive Patterning for Fan-Out Heterogeneous Integration

Rapid growth of advanced FOWLP (fan-out wafer level packaging) or simply fan-out, is upon us as the industry moves from historical monolithic SoC (system on chip) scaling to multi-die architectures using chiplets, tiles, dielets or whatever they’re called. The emerging multi-die devices can be either homogeneous or heterogeneous or combinations of both and are being driven by today’s most advanced applications including 5G, AI, autonomous driving as well as the Internet of Things. In this paper, we will explore the use of LDI (laser direct imaging) in combination with Adaptive Patterning® as a platform for photo lithography in support of this ever more complicated packaging integration. LDI is not new to the wafer level packaging industry since Deca first introduced the concept in 2010 and went to production in 2011 in support of WLCSP (wafer level chip scale packaging). Deca collaborated with an LDI technology leader in the PCB industry, Hitachi Via Mechanics (now ADTEC) to drive the technology to the precision required for wafer level packaging, a novel concept at the time. With the long-term vision of Adaptive Patterning in mind for embedded die structures such as M-Series™ fan-out, Deca utilized the advantages of rapid design-to-manufacturing in a mask-less environment and elimination of photomask costs as initial value drivers for WLCSP. The mask-less environment further allowed designers the opportunity to change layout attributes such as thieving structures for plating, RDL routing for modeling and more in real-time. Using digital masks allowed time and expense savings with the avoidance of initial tooling cost and storage. The key challenge is using LDI photolithography was the 405nm wavelength of the approach. Conventional wafer level packaging photoresists and photo imageable dielectrics were generally designed for either broadband or i-line exposure. Some of the broadband materials performed well with LDI, while Deca worked with several leading manufacturers to develop new photo-activation packages tailored for 405nm sensitivity. A combination of classic spin-on materials as well as novel dry film photoresists were successfully used in product qualifications and high-volume production. The process flow for dry film photoresist is different than liquid spin on. The dry film process consists of lamination, exposure, coversheet removal followed by develop. Typical throughput on a lamination tool is between 40 to 60 wafers per hour and not dependent on resist thickness. The conversion time from a standard 7 to 15µm RDL film to a 50 to 150µm Cu Pillar film can be accomplished in less than 15minutes. The advantages of a dry film include high throughput of greater than 100 wafer per hour for RDL steps with imaging down to 8µm, elimination of harmful solvents, waste handling of liquid photoresist, edge bead removal and associated film thickness variation due to resist swelling. Lower cost per wafer was another key factor in utilizing dry films with LDI over liquid resist. Current dry film engineering data suggests strong imaging performance down to 4µm at the 405nm wavelength with additional work underway on 2µm and finer features. The resolution of an optical system is dependent on exposure wavelength and NA (numerical aperture). Conventional photo steppers improve their imaging performance with higher and higher levels of NA rather than migrating to shorter wavelengths due to the use of cost-effective Hg lamps. The disadvantage of high NA steppers is the reduction in DOF (depth of focus). LDI offers a high DOF due to its inherent low NA, often 2x or greater DOF as compared to steppers. A higher DOF becomes critical as linewidths are scaled ever smaller upon the inherent imperfect planarity of organic FOWLP structures. A new generation of LDI tools are coming to market with enhanced capability to achieve 2µm lines and spaces and below utilizing 405nm or mixed wavelengths including 375nm. The shorter wavelength option opens the door for using more broadly available i-line sensitive materials. A breakthrough capability of LDI is the elimination of reticle size limits since there are no glass photomasks used in the process. Industry leading steppers are forced to use reticle stitching as package body size grows above the typical range of 16mm to 24mm. Several recent customer-driven designs for heterogeneous integration exceed 35mm on a side requiring multiple levels of reticle stitching which significantly reduces factory throughput driving up product cost. Using Adaptive Patterning design tools including AP Studio, product designers are limited only by the physical wafer or panel size where packages devices could grow to 300mm x 300mm if desired using a 600mm x 600mm manufacturing format. Another key LDI advantage is the ability to utilize a unique optimized design per wafer to precisely overcome embedded die shift related to natural variation in die placement and compression molding. Adaptive Patterning design tools are utilized by package designers to establish rules for Adaptive Alignment, Adaptive Routing or Adaptive Metal Fill for each package design. Within the presentation, the complete Adaptive Patterning process will be explained for a straightforward understanding of how complex heterogeneous multi-chiplet systems can be constructed in a cost-effective manner with optimum design rules and assurance of high yields in manufacturing. A survey of currently available LDI tools will be presented and a few examples of advanced M-Series fan-out technologies based heterogeneous chiplet-based products designed for LDI and Adaptive Patterning will be shared.

Influence of Rigid Carrier Substrates & its Release Layer on Ultra Fine Pitch chip last FO-WLPs

In recent years the leading-edge product enablers in Wireless Connectivity for WiFi & Bluetooth, Wearable HD Modules, Artificial Intelligence (AI), Application Processors etc. require ultra-high density chip packaging device using heterogenous integration to constructing the SiP modules. In order to meet their requirements, fan-out chip last WLP – having its redistribution layer (RDL) constructed first – is definitely the solution of choice to assemble devices in such advanced packaging platforms. This approach further eliminates known good die (KGD) loss risk, resulting in higher assembly yield and lower cost. Rigid carrier substrate and the release layer placed on top of it influences the process yield of fan-out chip last WLP. It gets more challenging when ultra-fine pitch redistribution layers (RDL) are required. This paper focuses on the influence of release layer on quality of narrow line & space RDL, as well as on the separation force during debonding. It further describes an optimized solution through HRDP® (High Resolution Debondable Panel) technology, which is the most compatible carrier to fabricate the leading-edge fan-out chip last process. The HRDP® carrier is offered in various dimensions and thicknesses as round wafers and square/rectangular panels with glass or silicon to match customer requirements. This is made of 100% inorganic material, which helps to improve interfacial stresses and facilitates debonding. During processing, this inorganic release layer (IRL) demonstrates higher chemical resistance and heat resistance than alternative technology such as the laser lift-off (LLO) type carrier.

FOWLP Thermal Debonding: Easing Manufacturing Constraints

Fan-out wafer level packaging enables System-in-package (SiP) and other forms of heterogenous integration. Multi-die configuration or passives for SiP alters the warpage profile of the wafer significantly. Wafers with square-shaped dies typically have bowl or dome type deformations. Wafers with rectangular-shaped dies tend to be deformed in a parabolic shape. However, as the packaging advances to different and more sophisticated technologies, the different chip sizes in one wafer adds complexity to the base structure, which leads to an unpredictable warpage profile and a higher warpage magnitude. Downstream equipment post wafer reconstruction needs to be able to handle this change in magnitude and profile since this could otherwise cause difficulties in high volume production and result in lower yield. The process step that requires the wafer to be placed onto chucks will result in vacuum failure and, if not modified to handle high warpage, the transport mechanism can result in wafer excursion and machine downtime. However, these modifications would require a costly redesign of the machine transport system, handling system, and end effectors. A less cost-intensive solution would be to ensure that the incoming wafer post reconstruction has minimum warpage. Thermal debonding is the last process of the wafer reconstruction flow and it acts as launchpad for layer build-up. It is in this step that warpage is inevitable as the wafer is released from the carrier. Thus, it is essential to have a warpage level that is manageable by these succeeding processes. This paper addresses the issue of warpage in Fan-out Wafer Level Packaging and presents a solution that lessens the warpage in the thermal debonding stage. The efficient processing of warped wafers is critical for the development of Fan-out and the transition to high volume manufacturing of these chips.

Selective Copper Electrodeposition for Redistribution Layer by Varying Concentration and Agitation of Janus Green B

A fine-pitch redistribution layer (RDL) for high-performance devices in a fan-out wafer-level package (FOWLP) is required in semiconductor packaging technology. The damascene process for fine-pitch RDL has been studied for several years, which has been introduced to overcome the etching problems. Although surface planarization for removing overburden is necessary for the damascene process in RDL, it adds high cost to the FOWLP process. Selective Cu electrodeposition is a method used to prevent overburden. Janus Green B (JGB) is utilized as a leveler in Cu electrodeposition and has properties that depend on concentration and agitation. These properties affected the Cu deposition rate according to the pattern position. Thus, the electrochemical properties of JGB were investigated based on the concentration of JGB and agitation. Furthermore, the effect of JGB on the crystalline structure of the Cu film was examined. Additionally, changes in the growth behavior of the Cu nuclei caused by JGB were observed during the initial stage of chronoamperometry. Based on these results, selective Cu electrodeposition was successfully performed on the patterned substrate using the difference in the concentration of JGB and agitation.

A Wideband Co-Linearly Polarized Full-Duplex Antenna-in-Package With High Isolation for Integrated Sensing and Communication

In this letter, a novel co-linearly polarized full-duplex antenna-in-package (AiP) with high Tx/Rx isolation and wide decoupled bandwidth is proposed for integrated sensing and communication (ISAC). Fan-out wafer-level packaging technology is employed, and the preparation process is discussed in details. To improve Tx/Rx isolation, the current direction of the patch elements is orthogonal to that of the feeding ports. Two identical 1×2 patch antenna arrays are used as Tx and Rx antennas, respectively. To further suppress mutual coupling, a decoupling loop is proposed to enhance Tx/Rx isolation. In addition, a wideband full-duplex AiP with high isolation and wide decoupled bandwidth is also proposed by using the parasitic technique and the proposed decoupling method. Prototypes are fabricated and measured to verify the proposed AiPs. The measurement results demonstrate that the proposed AiP possesses the merits of high Tx/Rx isolation (up to 53 dB), wide isolation bandwidth (up to 9.2%) and low cost, providing a foundation for chip-level applications in ISAC.

(Invited) Improvements in Thermal Budget and Film Properties Using Low Pressure Cure Technology for Advanced 3D Integration Packaging

3D advanced integration with Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP) offers multiple benefits: heterogenous chip design and stacking, increased interconnect density, and improved performance. However, it also brings new requirements for more compact form factors, low thermal budget materials and processing, and lower cost. The materials, process, and fabrication of heterogenous integration on redistribution layers (RDLs) consisting of metal and polymer dielectrics have become important enablers of the move to advanced packaging applications. To achieve the low-stress and low-cost benefits required by advanced integrated devices, thermal budgets must be reduced throughout the heterogenous integration flow -- including the dielectric curing step, which demands the use of low temperature processing and reduced cure times.In this presentation, the low temperature and low pressure thermal polymerization of dielectric polyimides used for redistribution layers (RDLs) is reviewed. Specifically, this presentation illustrates the significant impact of the low pressure cure process in reducing temperature (20° to 50° lower) and cure times (up to a 50% reduction) while providing better mechanical (elongation%, tensile strength, Young’s modulus), thermal (TG, Td 1%, Td 5%), and electrical (Dk, Df, dielectric breakdown strength - DBS) properties for different types of dielectric polyimides, including the Fujifilm LTC-9300 series, the Asahi BL-300 series, and the Toray LT-8300 and PW-1500 series. The post-curing polymerization ratio (FT-IR) and film stress were studied and are described. Finally, a proposed mechanism for the described dielectric polyimides’ polymerization under reduced pressure is discussed.Ongoing developments in design, materials, process and fabrication for FOWLP and FOPLP devices continue to drive progress in 3D heterogenous integration. This study of thermal processing of dielectric polyimides at low pressure and shorter time demonstrates a promising technique to improve overall process flow by reducing thermal budget, stress, and cost.

Crack mechanism correlated with Sn grain orientations on Ni metal surface subjected to 1000 thermal shocks

With the rapid development of 3D packaging, it is of great practical significance to understand the failure mechanism of solder joints in heterogeneous integration devices. In this study, the grain orientation and microstructure evolution of SAC305 solder joints were investigated in thermal shock tests for fan-out wafer level packaging. The heterogenous evolution of microstructure in Sn–3Ag-0.5Cu (SAC305) solder joints was investigated using electron backscattered diffraction (EBSD) and nanoindentation analysis. When the thermal shock reaches 1000 cycles, the local deformation caused the heterolattices in the joint to rotate toward the corners due to the thermal expansion. During deformation, sub-grain formation is accompanied by an increase in dislocations, the accumulation of plastic slip, and the activation of slip systems. The energy stored by this deformation is released in the form of cracks. The work in this paper provides new insights into the early stages of grain orientation, microstructural deformations and the accumulation of stored energy associated with these deformations, providing a scientific basis for the application and failure analysis of large size fan-out welded joints in complex working conditions.